The present invention relates to a surface-mounting semiconductor device sealed in a resin package and having its terminals exposed on a bottom surface of the resin package.
FIG. 43 and FIG. 44 show a semiconductor device Y1 as an example of a conventional surface-mounting wire-type semiconductor device. FIG. 43 is a sectional view of the semiconductor device Y1. FIG. 44 is a perspective view of the semiconductor device Y1 taken on the side of a bottom surface.
The semiconductor device Y1 includes two first conductors 910, a second conductor 920, a semiconductor chip 930, wires 940 and a resin package 950. Each of the first conductors 910 includes a first terminal surface 911. The second conductor 920 includes two second terminal surfaces 921. The first terminal surfaces 911 and the second terminal surfaces 921 provide the semiconductor device Y1 with electrical connection with external terminals. The semiconductor chip 930 is mounted on the second conductor 920. The semiconductor chip 930 has a lower surface provided with a terminal (not illustrated) electrically connected with the second conductor 920. Each wire 940 provides electrical connection between a terminal (not illustrated) formed on an upper surface of the semiconductor chip 930 and one of the first conductors 910. The resin package 950 seals the first conductors 910, the second conductor 920, the semiconductor chip 930, and the wires 940 while exposing the first terminal surfaces 910 and the second terminal surfaces 921. The two first terminal surfaces 911 and the two second terminal surfaces 921 are in a same plane, on a bottom surface 950a of the resin package 950.
According to such a semiconductor device Y1, in order to avoid electrical discharge between mutually opposed conductors, as shown in FIG. 43, the first conductors 910 and the second conductor 920 must to be spaced from each other by a distance L6, which must be greater than a certain minimum value. This requirement poses a problem to size reduction of the conventional semiconductor device Y1.
There is another problem. Specifically, if the semiconductor device Y1 is a surface-mounting transistor for example, the number and the size of the terminals are standardized in general, in accordance with the size of the semiconductor device Y1. If a size (e.g. a length L7) of the semiconductor device Y1, a size (e.g. a length L8) of the first terminal surface 911, and so on are provided in accordance with the standards, a size (e.g. a length L9) of the second conductor 920 must be relatively small according to the conventional semiconductor device Y1. This limits a size (e.g. a length L10) of the semiconductor chip 930 mountable to the second conductor 920, leading to an occasional problem that a desired function cannot be achieved within a single semiconductor device.
FIG. 45 and FIG. 46 show a semiconductor device Y2 as an example of a conventional surface-mounting wireless-type semiconductor device. FIG. 45 is a perspective view of the semiconductor device Y2. FIG. 46 is a perspective view of the semiconductor device Y2 taken from the opposite side as in FIG. 45.
The semiconductor device Y2 includes a first conductor 910, a second conductor 920, a semiconductor chip 930, and a resin package 950. The first conductor 910 has a bent structure including a first portion 915, a second portion 916, and a third portion 917 in between. The first portion 915 is bonded to an electrode (not illustrated) provided on an upper surface of the semiconductor chip 930. The second portion 916 includes two first terminal surfaces 911. The second conductor 920 includes two second terminal surfaces 921. The semiconductor chip 930 is mounted on the second conductor 920. The semiconductor chip 930 has a lower surface provided with a terminal (not illustrated) which is electrically connected with the second conductor 920. According to the semiconductor device Y2, the resin package 950 seals the first conductor 910, the second conductor 920, the semiconductor chip 930 while exposing the first terminal surfaces 911 and the second terminal surfaces 921. The two first terminal surfaces 911 and the two second terminal surfaces 921 are in a same plane on a bottom surface 950a of the resin package 950.
According to the semiconductor device Y2, which includes the first conductor 910 as shown in FIG. 45 and FIG. 46, the third portion 917 provides electrical connection between the first terminal surfaces 911 and the electrode on the upper surface of the semiconductor chip 930, and it is difficult to dispose this third portion along a side surface 950b of the resin package 950, closely to the side surface 950b. Therefore, according to the semiconductor device Y2 of a given size, size of usable semiconductor chip 930 is limited. Likewise, the size of the semiconductor device Y2 must be increased if the semiconductor chip 930 to be mounted is larger than the second conductor 920.
The semiconductor device Y2 is conventionally made from a lead frame 960 as shown in FIG. 47. The lead frame 960 includes a first region 910A formed with a plurality of rectangular-shaped first conductor lands 910a each to serve as the first conductor 910, and a second region 920A formed with a plurality of second conductor lands 920a each to serve as the second conductor 920. In the manufacture of the semiconductor device Y2, each first conductor land 910a undergoes a press-folding step, for formation of the first portion 915, the second portion 916 and the third portion 917. Next, a semiconductor chip 930 is mounted on each second conductor land 920a. Next, the first region 910A is pivoted around a pair of bridge portions 961 and is overlapped onto the second region 920A, into a state as shown in FIG. 48, in a single unit of semiconductor device formation area.
In order to reliably bond the first conductor land 910a with the semiconductor chip 930 after the first region 910A is overlapped onto the second region 920A, during the above-mentioned press-folding step performed to the first conductor land 910a, the first conductor land 910a is folded so that the first portion 915 and the third portion 917 make an acute angle slightly smaller than shown in FIG. 48. If the first conductor land 910a is folded as such, during the overlapping step shown in FIG. 48, the first conductor land 910a urges the semiconductor chip 930 in a direction indicated by Arrow A.
However, the first conductor land 910a has a fixed base end 910axe2x80x2. Therefore, if there is a large force acting in the direction indicated by Arrow A due to a bent of a border region between the first portion 915 and the third portion 917, a force develops which tends to increase the acute angle between the second portion 916 and the third portion 917. As a result, the border region between the second portion 916 and the third portion 917 is sometimes raised as indicated by Arrow B. If the border region between the second portion 916 and the third portion 917 is raised, the first terminal surface 911 of the second portion 916 is raised accordingly. It is conjectured that such a phenomenon is caused mainly by excessively high stiffness of the border region between the third portion 917 and the first portion 915, which generates a large repelling force in the first conductor land 910a when a force is applied which could deform the shape of the border region.
If such a state is not corrected before the semiconductor chip 930 and the other components are sealed into the resin package 950, the resin material invades into an underside of the first terminal surfaces 911 of the second portion 916. Specifically, a resulting semiconductor device Y2 has a resin package 950 having a bottom surface 950a which does not expose the first terminal surfaces 911 properly. Such a semiconductor device Y2 cannot be surface mounted properly, and therefore must be discarded, and this results in a decreased yield in the manufacture of the semiconductor device Y2.
The present invention was made under such a circumstance, and it is therefore an object of the present invention to eliminate or reduce the conventional problems, to provide a semiconductor device which is sufficiently small and surface-mountable, and to provide a method of making the same.
A first aspect of the present invention provides a semiconductor device. This semiconductor device comprises: a first conductor including a first terminal surface; a second conductor placed by the first conductor and including a second terminal surface facing a same direction as does the first terminal surface; a third conductor connected with the first conductor; a semiconductor chip including a first surface and a second surface away from the first surface, the first surface being provided with a first electrode electrically connected with the first conductor via the third conductor, the second surface being provided with a second electrode electrically connected directly with the second conductor, the semiconductor chip being bonded to the first conductor and the second conductor via the second surface; and a resin package sealing the first conductor, the second conductor, the third conductor and the semiconductor chip while exposing the first terminal surface and the second terminal surface.
Preferably, the third conductor includes a first portion connected with the first electrode and bonded to the first surface, and a second portion generally vertical to the first portion and connected with the first conductor.
Preferably, the first portion of the third conductor entirely covers the first surface of the semiconductor chip.
A second aspect of the present invention provides a method of making a semiconductor device. This method uses a lead frame including a semiconductor device formation area formed with a first conductor land and a second conductor land. The first conductor land has a first terminal surface, whereas the second conductor land is by the first conductor land and has a second terminal surface facing in a same direction as does the first terminal surface. The method comprises: a step of placing a semiconductor chip including a first surface formed with a first electrode and a second surface facing away from the first surface and formed with a second electrode, on the first conductor land and the second conductor land, via the second surface; a step of placing a third conductor so as to contact the first conductor land and the first surface of the semiconductor chip; a step of electrically connecting between the first conductor land and the third conductor, between the second electrode of the semiconductor chip and the second conductor land, and between the first electrode of the semiconductor chip and the third conductor; a step of sealing the first conductor, the second conductor, the third conductor and the semiconductor chip with a resin package while exposing the first terminal surface and the second terminal surface; and a step of cutting the first conductor land and the second conductor land from the lead frame.
A third aspect of the present invention provides another semiconductor device. This semiconductor device comprises a first conductor including a first terminal surface; a second conductor placed by the first conductor and including a second terminal surface facing in a same direction as does the first terminal surface; a third conductor connected with the first conductor; a semiconductor chip including a first surface and a second surface away from the first surface, the first surface being provided with a first electrode electrically connected with the first conductor via the third conductor, the second surface being provided with a second electrode electrically connected directly with the second conductor, the semiconductor chip being bonded to the first conductor and the second conductor via the second surface; and a resin package sealing the first conductor, the second conductor, the third conductor and the semiconductor chip while exposing the first terminal surface and the second terminal surface. The first conductor has a first thin portion opposed to the second conductor and receded toward the first terminal surface. The second conductor has a second thin portion opposed to the first conductor and receded from the second terminal surface.
Preferably, the third conductor includes a first portion connected with the first electrode and bonded to the first surface, and a second portion generally vertical to the first portion and connected with the first conductor.
Preferably, the first portion of the third conductor entirely covers the first surface of the semiconductor chip.
A fourth aspect of the present invention provides a method of making a lead frame from a metal plate having a first surface, second surface facing away therefrom, and a thickness as between the first surface and the second surface. The lead frame includes a first conductor land and a second conductor land opposed to each other at a space. The method comprises: a step of performing a first etching to a first region in the first surface, to a middle of the thickness; and a step of performing a second etching to a second region in the second surface, to a middle of the thickness. The second region is displaced with respect to the first region. The first etching and the second etching form a gap between the first conductor land and the second conductor land. The first etching forms a first thin portion receding from the first surface, on the first conductor land at a region opposed by the second conductor land. The second etching forms a second thin portion receding from the second surface, on the second conductor land at a region opposed by the first conductor land.
A fifth aspect of the present invention provides another semiconductor device. This semiconductor device comprises: a first conductor including a first portion, a second portion having a first terminal surface, and a third portion connecting the first portion and the second portion; a second conductor placed by the second portion, including a second terminal surface facing in a same direction as does the first terminal surface; a semiconductor chip including a first surface and a second surface away from the first surface, the first surface being provided with a first electrode electrically connected with the first portion, the second surface being provided with a second electrode electrically connected with the second conductor, the semiconductor chip being bonded to the second conductor via the second surface; and a resin package sealing the first conductor, the second conductor and the semiconductor chip while exposing the first terminal surface and the second terminal surface. The first portion and the third portion share a bent first border region. The second portion and the third portion share a bent second border region. The third portion is smaller than the first portion in width at the first border region, or the third portion is smaller than the second portion in width at the second border region.
Preferably, the first conductor has a shape of letter J, U or C, enclosing at least part of the semiconductor chip.
Preferably, the first portion of the first conductor entirely covers the first surface of the semiconductor chip and is bonded to the semiconductor chip.
A sixth aspect of the present invention provides another method of making a semiconductor device. This method uses a lead frame including a first region and a second region. The first region is formed with a first conductor land having a first portion, a second portion having a first terminal surface and a third portion connecting the first portion and the second portion. The second region is formed with a second conductor land having a second terminal surface. The method comprises: a step of folding the first conductor land, at a first border region between the first portion and the third portion and at a second border region between the second portion and the third portion; a step of placing a semiconductor chip on the first portion of the first conductor land, or on the second conductor land; a step of overlapping the first region and the second region with each other, via the semiconductor chip; a step of electrically connecting between the first portion of the first conductor land and the semiconductor chip and between the second conductor land and the semiconductor chip; a step of sealing the first conductor, the second conductor and the semiconductor chip with a resin package while exposing the first terminal surface and the second terminal surface; and a step of cutting the first conductor land and the second conductor land from the lead frame. The third portion is smaller than the first portion in width at the first border region, or the third portion is smaller than the second portion in width at the second border region.
Preferably, the folding of the first conductor land in the step of folding the first conductor land leaves the second portion to extend from the third portion in a direction away from the first portion.
Preferably, the second portion includes a pair of projections each having the first terminal surface. The third portion connects to the second portion at a region between the pair of projections. The second border region is between the region sandwiched by the pair of projections and the third portion. The width of the third portion at the second border region is smaller than a distance between the pair of projections.
Preferably, the second border region is formed with a pair of cutouts extending in an opposite direction from the extending direction of the third portion, at an interval corresponding to the width of the third portion. The pair of cutouts is utilized for folding the third portion with respect to the second portion, in the step of folding the first conductor land.
Preferably, the third portion is thinner than the first portion in the first border region.
Preferably, the third portion is thinner than the second portion in the second border region.